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SPEAR-09-H022
SPEArTM Head ARM 926, 200K customizable eASICTM gates, large IP portfolio SoC
PRELIMINARY DATA
Features
ARM926EJ-S - fMAX 266 MHz, 32 KI - 16 KD cache, 8 KI - KD tcm, ETM9 and JTAG interfaces 200K customizable equivalent ASIC gates (16K LUT equivalent) with 8 channels internal DMA high speed accelerator function and 112 dedicated general purpose I/Os Multilayer AMBA 2.0 compliant Bus with fMAX 133 MHz Programmable internal clock generator with enhanced PLL function, specially optimized for E.M.I. reduction 16 KB single port SRAM embedded Dynamic RAM interface: 16 bit DDR, 32 / 16 bit SDRAM SPI interface connecting serial ROM and Flash devices 2 USB 2.0 Host independent ports with integrated PHYs USB 2.0 Device with integrated PHY Ethernet MAC 10/100 with MII management interface 3 independent UARTs up to 115 Kbps (Software Flow Control mode) I2C Master mode - Fast and Slow speed 6 General Purpose I/Os

PBGA420
ADC 8 bits, 230 Ksps, 16 analog input channels Real Time Clock WatchDog 4 General Purpose Timers Operating temperature: - 40 to 85 C Package: PBGA 384+36 6R (23x23x2.16 mm)

Overview
SPEAr Head is a powerful digital engine belonging to SPEAr family, the innovative customizable System on Chips. The device integrates an ARM core with a large set of proven IPs (Intellectual Properties) and a configurable logic block that allows very fast customization of unique and/or proprietary solutions, with low effort and low investment. Optimized for embedded applications.

Order codes
Part number SPEAR-09-H022 Op. Temp. range, C -40 to 85 Package PBGA420 (23x23x2.16 mm) Packing Tray
December 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev 2 1/55
www.st.com
55
SPEAR-09-H022
Contents
1 2 3 Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 INTERNAL BUS STRUCTURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 INTERRUPT CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 MEMORY SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 HIGH SPEED CONNECTIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 LOW SPEED CONNECTIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 GENERAL POURPOSE I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ANALOG TO DIGITAL CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 REAL TIME CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 GENERAL PURPOSE TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CUSTOMIZABLE LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 4.2 FUNCTIONAL PIN GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SPECIAL IOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2.1 4.2.2 USB 2.0 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
Power On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 SPEAr Head SW ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.1 5.1.2 BOOT PROCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 BOOTING SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6
IP Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1 6.2 ARM926EJ-S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CLOCK AND RESET SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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6.2.1 6.2.2 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 RESET AND PLL CHANGE PARAMETERS SEQUENCE . . . . . . . . . . . . . . 30
6.3
VECTORED INTERRUPT CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.1 6.3.2 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 INTERRUPTR SOURCES IN SPEAr Head . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.4
MULTI-PORT MEMORY CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.4.1 6.4.2 6.4.3 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 MULTI-PORT MEMORY CONTROLLER DELAY LINES . . . . . . . . . . . . . . . . 34 SSTLL PIN CONFIGRATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.5 6.6
SPI MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.6.1 6.6.2 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DMA CONTROL STATE MACHINE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.7 6.8 6.9 6.10 6.11
USB 2.0 HOST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.7.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
USB 2.0 DEVICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.8.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
ETHERNET MAC 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.11.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.11.2 I2C OPERATING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.11.3 I2C FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.12 6.13
GENERAL POURPOSE I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.13.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.13.2 ADC OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.14 6.15 6.16 6.17
WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 REAL TIME CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 GENERAL POURPOSE TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 CUSTOMIZABLE LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.17.1 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.17.2 CUSTOM PROJECT DEVELOPMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.17.3 CUSTOMIZATION PROCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.17.4 POWER ON SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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6.17.5 BITSTREAM DOWNLOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.17.6 CONNECTION STARTUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.17.7 PROGRAMMING INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.1 7.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DC ELETTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7.2.1 7.2.2 SUPPLY VOLTAGE SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 I/O VOLTAGE SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8 9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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1 Reference Documentation
1
Reference Documentation
[1] [2] [3] [4] [5] [6] [7] [8] [9] ARM926EJ-S - Technical Reference Manual AMBA 2.0 Specification EIA/JESD8-9 Specification USB2.0 Specification OCHI Specification ECHI Specification UTMI Specification USB Specification IEEE 802.3 Specification
[10] I2C - Bus Specification
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2 Product Overview
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2
Product Overview
SPEAr Head is a powerful System on Chip based on 110nm HCMOS and consists of 2 main parts: an ARM based architecture and an embedded customizable logic block. The high performance ARM architecture frees the user from the task of developing a complete RISC system. The customizable logic block allows user to design custom logic and special functions. SPEAr Head is optimized for embedded applications and thanks to its high performance can be used for a wide range of different purposes. Main blocks description: 1. CPU: ARM926EJ-S running at 266 MHz. It has: - - - - - - - - - 2. MMU 32 KB of instruction CACHE 16 KB of data CACHE 8 KB of instruction TCM (Tightly Coupled Memory) 8 KB of data TCM AMBA Bus interface Coprocessor interface JTAG ETM9 (Embedded Trace Macro-cell) for debug; large size version.
Main Bus System: a complete AMBA Bus 2.0 subsystem connects different masters and slaves. The subsystem includes: - - AHB Bus, for high performance devices APB Bus, for low power / lower speed devices connectivity
- Bus Matrix, for improving connection between the peripherals Parts of these buses are available for the customizable logic block. 3. Clock and Reset System: fully programmable block with: - - - 4. 5. 6. Separated set up between clocks of AHB Bus and APB Bus peripherals E.M.I. reduction mode, replacing all traditional drop methods for Electro-Magnetic Interference Debug mode, compliant with ARM debug status
Interrupt Controller: the Interrupt Controller has 32 interrupt sources which are prioritized and vectorized. On-chip memory: 4 independent static RAM cuts, 4 KB each, are available. They can be used on AHB Bus or directly by the custom logic. Dynamic Memory Controller: it is a Multi-Port Memory Controller which is able to connect directly to memory sizes from 16 to 512 Mbits; the data size can be 8 or 16 bits for both DDR and SDRAM, also 32 bits for SDRAM. The external data bus can be maximum 32 bit wide at maximum clock frequency of 133 MHz and have up to 4 chip selects; the accessible memory is 256 MB. Internally it handles 7 ports supporting the following masters: AHB Bus, Bus Matrix, 2 USB 2.0 Hosts, USB 2.0 Device, Ethernet MAC, eASIC MacroCell.
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2 Product Overview
The Multi-Port Memory Controller block has a programmable arbitration scheme and the transactions happen on a different layer from the main bus. 7. Serial Peripheral Interface: it allows a serial connection to ROM and Flash. The block is connected as a slave on the main AHB Bus, through the Bus Matrix. The default bus size is 32 bit wide and the accessible memory is 64 MB at a maximum speed of 50 MHz USB 2.0 Hosts: these peripherals are compatible with USB 2.0 High-Speed specification. They can work simultaneously either in Full-Speed or in High-Speed mode. The peripherals have dedicated channels to the Multi-Port Memory Controller and 4 slave ports for CPU programming. The PHYs are embedded. USB 2.0 Device: the peripheral is compatible with USB 2.0 High-Speed specifications. A dedicated channel connects the peripheral with the Multi-Port Memory Controller and registers and internal FIFO are accessible from the CPU through the main AHB Bus. An USB-Plug Detector block is also available to verify the presence of the VBUS voltage. The port is provided with the following endpoints on the top of the endpoint 0: - 3 bulkin / bulkout endpoints - 2 isochronous endpoints. The PHY is integrated. 10. Ethernet Media Access Control (MAC) 10/100: this peripheral is compatible with IEEE 802.3 standard and supports the MII management interface for the direct configuration of the external PHY. It is connected to the Multi-Port Memory Controller through a dedicated channel. The Ethernet controller and the configuration registers are accessible from the main AHB Bus. 11. ADC: 8 bit resolution, 230 Ksps (Kilo-sample per second), with 16 analog input channels. Connected to APB bus. 12. UARTs: 3 independent interfaces, up to 115 Kbps each, support Software Flow Control. Connected to APB bus. 13. I2C supporting Master mode protocol in Low and Full speed. Connected to APB bus. 14. 6 General Purpose I/O signals are available for user configuration. Connected to APB bus. 15. Embedded features: programmable Clock System and Dithered function, Real Time Clock, Watchdog, 4 General Purpose Timers. All blocks are interfaced with APB Bus. 16. Customizable Logic: it consists of an embedded macro where it is possible to map up to 200K equivalent ASIC gates. The same logic can be alternatively used to implement 32 KBytes of SRAM. Logic gates and RAM bits can be mixed in the same configuration so that processing elements, tightly coupled with embedded memories, can be easily implemented. The MacroCell has 2 dedicated buses, each of them connected with a 4 channel DMA in order to speed up the data flow with the main memories. 8 interrupt lines and 112 dedicated general purpose I/Os are available. To allow a simple development of project, customizable logic can be emulated by an external FPGA, where customer can map his logic; FPGA is easy linkable and keeps the access to all on-chip and I/Os interfaces of the macro.
8.
9.
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2 Product Overview
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Figure 1.
Block diagram
CUSTOMER I/Os
Dithered
ARM926EJ-S
System Clock
Real Time VIC Clock
200K eASICTM gates
WdT
USB 2.0
H I G H
4 GPTs
A H B
4 KB SRAM
4 KB SRAM
4 KB SRAM
4 KB SRAM
A P B
L O
Host + PHY
B
S P E E D
u USB 2.0 Host + PHY s
gDMA0
gDMA1
Programmable Interface
B u s
3 UARTs
W
S P
Bus Matrix IC
E E D
C O N N E C T I V I T Y
USB 2.0
C
Device + PHY
Bus Bridge 6 GP I/Os
O N N E C ADC 8 bits, T I V I T Y
Ethernet MAC
Multi-Port Memory CTRL SPI for ROM, Flash
16 channels
MEMORY
INTERFACES
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3 Features
3
3.1
Features
CPU

ARM926EJ-S RISC Processor fMAX 266 MHz (downward scalable) Virtual address support with MMU 32 KB instruction CACHE (4 way set associative) 16 KB data CACHE (4 way set associative) 8 KB instruction TCM 8 KB data TCM Coprocessor interface JTAG ETM9 (rev 2.2), large size FIFO
3.2
INTERNAL BUS STRUCTURES

Multilayer structure AMBA 2.0 compliant fMAX 133 MHz High speed I/Os with embedded DMA function
3.3
CLOCK SYSTEM

Programmable clock generator PLL with E.M.I. reduction Low Jitter PLL for USB 2.0
3.4
INTERRUPT CONTROLLER

IRQ and FIQ interrupt generations Support up to 32 standard interrupts Support up to 16 vectored interrupts Software interrupt generation
3.5
MEMORY SYSTEM
MEMORY ON CHIP 16 KBytes single-port SRAM connected to eASIC MacroCell. It can be used on AHB Bus or directly by the custom logic.
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SPI

4 chip selects for asynchronous devices (ROM, Flash) Supports Normal mode 20 MHz and Fast mode 50 MHz AHB slave Accessible memory: 64 MB 8 / 16 / 32 bit widths Programmable wait states
MULTI-PORT MEMORY CONTROLLER

Maximum clock frequency 133 MHz Support up to 7 AHB master requests AHB slave Support for 8, 16 and 32 bit wide SDRAM Support for 8 and 16 bit wide DDRAM 4 chip selects Physical addressable memory up to 256 MB Memory clock tuning to match the timing of different memory vendors
3.6
HIGH SPEED CONNECTIVITY
USB 2.0 HOST

2 USB 2.0 Host controllers with their UTMI PHY port embedded High-Speed / Full-Speed / Low-Speed modes USB 2.0 complaint DMA FIFO 4 AHB slaves for configuration and FIFO access 4 AHB masters for data transfer
USB 2.0 DEVICE

UDC 2.0 controller with embedded PHY High-Speed / Full-Speed / Low-Speed modes USB 2.0 complaint USB Self-Power mode DMA FIFO AHB master interface for DMA transfer AHB slaves for: configuration, FIFO access, Plug autodetect Endpoints on the top of endpoint 0: 3 bulkin / bulkout, 2 isochronous
ETHERNET 10/100

MAC110 controller compliant with IEEE 802.3 standard Supporting MII 10/100 Mbits/s MII management protocol interface TX FIFO (512x36 Dual Port)
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3 Features
RX FIFO (512x36 Dual Port) AHB DMA master connected to memory system AHB slave for configuration
3.7
LOW SPEED CONNECTIVITY
UART

Support for 8 bit serial data TX and RX Selectable 2 / 1 Stop bits Selectable Even, Odd and No Parity Parity, Overrun and Framing Error detector Max transfer rate: 115 Kbps
I2C

Standard I2C mode (100 KHz) / Fast I2C mode (400 KHz) Master interface only Master functions control all I2C bus specific sequencing, protocol, arbitration and timing Detection of bus errors during transfers
3.8
GENERAL POURPOSE I/Os
6 programmable GP I/Os
3.9
ANALOG TO DIGITAL CONVERTER

8 bit resolutions 230 Ksps 16 analog input channels (0 - 3.3 V) INL 1 LSB DNL 0.5 LSB Programmable conversion speed - minimum conversion time 4.3 s
3.10
REAL TIME CLOCK

Real time clock-calendar (RTC) 14 digit (YYYY MM DD hh mm ss) precision Clocked by 32.768 KHz low power clock input Separated power supply (1.2 V)
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3.11
WATCHDOG TIMER

Programmable 16 bit Watchdog timer with reset output signal (more than 200 system clock period to initial peripheral devices) Programmable period 1 ~ 10 sec For recovery from unexpected system Hang-up
3.12
GENERAL PURPOSE TIMERS

Four 16 bit timers with 8 bit prescaler Frequency range: 3.96 Hz - 66.5 MHz Operating mode: Auto Reload and Single Shot
3.13
CUSTOMIZABLE LOGIC

200K equivalent ASIC gate configurable either custom logic or 32 KBytes single-port SRAM or mixing logic and RAM 2 dedicated buses, each of them connected with a 4 channel DMA 8 interrupt lines (level type) available 112 dedicated GP I/Os Single VIA mask configurable interconnections Emulation by an external FPGA, keeping on-chip and I/O interfaces
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4 Pin Description
4
4.1
Pin Description
FUNCTIONAL PIN GROUPS
With reference to Figure 14. Package schematic - Section 8, here follows the pin list, sorted by their belonging IP. All supply and ground pins are classified as power signals and gathered in the Table 2.
Table 1.
Group
Pin description by functional groups
Signal Name AIN[0] AIN[1] AIN[2] AIN[3] AIN[4] AIN[5] AIN[6] AIN[7] Ball V20 V19 V18 V17 V16 V15 V14 V12 Input ADC analog input channel V11 V10 V9 V8 U22 U21 U20 U19 V13 E22 E21 Input TEST2 D22 D21 Y5 G4 G3 Input I/O eASIC general purpose IO eASICGP_IO[1] Enable / disable PLL bypass TTL Schmitt trigger input buffer, 3.3 V capable TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability TTL input buffer, Test configuration port. For the functional mode they have 3.3 V capable, to be set to 0 with Pull Down Output ADC output test pad Analog buffer, 3.3 V capable Direction Function Pin Type
ADC
AIN[8] AIN[9] AIN[10] AIN[11] AIN[12] AIN[13] AIN[14] AIN[15] TEST_OUT TEST0 TEST1
DEBUG
TEST3 PLL_BYPASS eASICGP_IO[0]
eASIC
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Table 1.
Group
Pin description by functional groups (continued)
Signal Name eASICGP_IO[2] eASICGP_IO[3] eASICGP_IO[4] eASICGP_IO[5] eASICGP_IO[6] eASICGP_IO[7] eASICGP_IO[8] eASICGP_IO[9] eASICGP_IO[10] eASICGP_IO[11] eASICGP_IO[12] eASICGP_IO[13] eASICGP_IO[14] eASICGP_IO[15] eASICGP_IO[16] eASICGP_IO[17] Ball G2 F5 F4 F3 F2 E9 E8 E7 E6 E5 E4 E3 E2 D8 D7 D6 D5 D4 D3 D2 C8 C7 C6 C5 C4 C3 C2 B8 B7 B6 B5 B4 B3 eASIC general purpose IO TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability Direction I/O Function Pin Type
eASIC
eASICGP_IO[18] eASICGP_IO[19] eASICGP_IO[20] eASICGP_IO[21] eASICGP_IO[22] eASICGP_IO[23] eASICGP_IO[24] eASICGP_IO[25] eASICGP_IO[26] eASICGP_IO[27] eASICGP_IO[28] eASICGP_IO[29] eASICGP_IO[30] eASICGP_IO[31] eASICGP_IO[32] eASICGP_IO[33] eASICGP_IO[34]
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Table 1.
Group
4 Pin Description
Pin description by functional groups (continued)
Signal Name eASICGP_IO[35] eASICGP_IO[36] eASICGP_IO[37] eASICGP_IO[38] eASICGP_IO[39] eASICGP_IO[40] eASICGP_IO[41] eASICGP_IO[42] eASICGP_IO[43] eASICGP_IO[44] eASICGP_IO[45] eASICGP_IO[46] eASICGP_IO[47] eASICGP_IO[48] eASICGP_IO[49] Ball B2 A8 A7 A6 A5 Direction Function Pin Type
A4 A3 A2 D9 C9 B9 A9 E10 D10 C10 B10 A10 E11 D11 C11 B11 A11 E12 D12 C12 B12 A12 E13 D13 C13 B13
I/O eASIC general purpose IO TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability
eASIC
eASICGP_IO[50] eASICGP_IO[51] eASICGP_IO[52] eASICGP_IO[53] eASICGP_IO[54] eASICGP_IO[55] eASICGP_IO[56] eASICGP_IO[57] eASICGP_IO[58] eASICGP_IO[59] eASICGP_IO[60] eASICGP_IO[61] eASICGP_IO[62] eASICGP_IO[63] eASICGP_IO[64] eASICGP_IO[65]
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4 Pin Description
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Table 1.
Group
Pin description by functional groups (continued)
Signal Name eASICGP_IO[66] eASICGP_IO[67] eASICGP_IO[68] eASICGP_IO[69] eASICGP_IO[70] eASICGP_IO[71] eASICGP_IO[72] eASICGP_IO[73] eASICGP_IO[74] eASICGP_IO[75] eASICGP_IO[76] eASICGP_IO[77] eASICGP_IO[78] eASICGP_IO[79] eASICGP_IO[80] Ball Direction Function Pin Type
A13 E14 D14 C14 B14 A14 E15 D15 C15 B15 A15 E16 D16 C16
B16 A16 E17 D17 C17 B17 A17 L18 K18 J18 H18 G18 F18 E18 D18 C18 B18 A18 J19 I/O eASIC general purpose IO TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability
eASIC
eASICGP_IO[81] eASICGP_IO[82] eASICGP_IO[83] eASICGP_IO[84] eASICGP_IO[85] eASICGP_IO[86] eASICGP_IO[87] eASICGP_IO[88] eASICGP_IO[89] eASICGP_IO[90] eASICGP_IO[91] eASICGP_IO[92] eASICGP_IO[93] eASICGP_IO[94] eASICGP_IO[95] eASICGP_IO[96] eASICGP_IO[97] eASICGP_IO[98]
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Table 1.
Group
4 Pin Description
Pin description by functional groups (continued)
Signal Name eASICGP_IO[99] eASICGP_IO[100] eASICGP_IO[101] eASICGP_IO[102] eASICGP_IO[103] eASICGP_IO[104] eASICGP_IO[105] eASICGP_IO[106] eASICGP_IO[107] Ball H19 G19 F19 E19 D19 C19 B19 eASIC general purpose IO A19 G20 F20 E20 D20 C20 B21 R18 G5 eAISC Program Interface out clock eASIC output clock TTL bidirectional buffer, 3.3 V capable, 8 mA drive capability TTL input buffer, 3.3 V capable with Pull Down I/O TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability Direction Function Pin Type
eASIC
eASICGP_IO[108] eASICGP_IO[109] eASICGP_IO[110] eASICGP_IO[111] eASIC_EXT_CLOCK eASIC_PI_CLOCK eASIC_CLK
CONFIG_DEVEL TX_CLK TXD[0] TXD[1] TXD[2] TXD[3] TX_EN CRS Ethernet COL RX_CLK RXD[0] RXD[1] RXD[2] RXD[3] RX_DV RX_ER
A20 J20 J21 J22 K19 K20 K21 K22 L19 L20
Input Input
External FPGA emulation mode Ethernet input TX clock Ethernet TX output data
Output
Ethernet TX enable Carrier sense input Collision detection input Ethernet input RX clock Input TTL bidirectional buffer, 5 V tolerant, 4 mA drive capability, with Pull Down
L21 L22 Ethernet RX input data M19 M20 M21 M22 Input Input Input Data valid on RX Data error detected
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Table 1.
Group
Pin description by functional groups (continued)
Signal Name Ball Direction Function Pin Type TTL bidirectional buffer, 5 V tolerant, 4 mA drive capability, with Pull Down
MDC Ethernet
N19
Output
Output timing reference for MDIO
MDIO GP_IO[0] GP_IO[1] GP_IO[2] GPI/Os GP_IO[3] GP_IO[4] GP_IO[5] SDA IC SCL
N20 T22 T21 T20
I/O
I/O data to PHY
General Purpose IO T19 R22 R21 N21 I2C serial data I/O
TTL bidirectional buffer, 3.3 V capable, 8 mA drive capability
N22
TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability, with Pull Up TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability, with Pull Up Oscillator 3.3 V capable TTL Schmitt trigger input buffer, 3.3 V capable
TDO
A21
Output
Jtag TDO
JTAG
TDI TMS RTCK TCK nTRST
A22 B20 B22 C21 C22 T1 U1 H4 AA12 Y12 W12 AB13 AA13 Y13 W13
Input Input Output Input Output Input Output Input
Jtag TDI Jtag TMS Jtag output clock Jtag clock Jtag reset 12 MHz input cristal 12 MHz output cristal Master reset
MASTER MCLK_in CLOCK MCLK_out MASTER MRESET RESET MPMCDATA[0] MPMCDATA[1] MPMCDATA[2] MPMC MPMCDATA[3] MPMCDATA[4] MPMCDATA[5] MPMCDATA[6]
I/O
DDR / SDRAM data
LVTTL / SSTL ClassII bidirectional buffer
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Table 1.
Group
4 Pin Description
Pin description by functional groups (continued)
Signal Name MPMCDATA[6] MPMCDATA[7] MPMCDATA[8] MPMCDATA[9] MPMCDATA[10] MPMCDATA[11] MPMCDATA[12] MPMCDATA[13] MPMCDATA[14] MPMCDATA[15] MPMCDATA[16] MPMCDATA[17] MPMCDATA[18] MPMCDATA[19] MPMCDATA[20] MPMCDATA[21] MPMCDATA[22] Ball W13 AA14 AA16 AB18 AB19 I/O AB20 AB21 AA21 AB22 AA22 AA18 AA17 Y22 Y21 Y20 Y19 Y18 Y17 I/O MPMCDATA[24] MPMCDATA[25] MPMCDATA[26] MPMCDATA[27] MPMCDATA[28] MPMCDATA[29] MPMCDATA[30] MPMCDATA[31] MPMCADDROUT[0] MPMCADDROUT[1] MPMCADDROUT[2] MPMCADDROUT[3] MPMCADDROUT[4] MPMCADDROUT[5] MPMCADDROUT[6] MPMCADDROUT[7] MPMCADDROUT[8] Y16 W22 W21 W20 W19 W18 W17 W16 AB8 AA8 Y8 W8 AB9 AA9 Y9 W9 AB10 Output DDR / SDRAM data LVTTL / SSTL ClassII bidirectional buffer SDRAM data TTL bidirectional buffer, 3.3 V capable, 8 mA drive capability DDR / SDRAM data LVTTL / SSTL ClassII bidirectional buffer Direction Function Pin Type
MPMC
MPMCDATA[23]
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Table 1.
Group
Pin description by functional groups (continued)
Signal Name MPMCADDROUT[9] MPMCADDROUT[10] MPMCADDROUT[11] MPMCADDROUT[12] MPMCADDROUT[13] MPMCADDROUT[14] nMPMCDYCSOUT[0] nMPMCDYCSOUT[1] nMPMCDYCSOUT[2] nMPMCDYCSOUT[3] MPMCCKEOUT[0] MPMCCKEOUT[1] MPMCCLKOUT[0] nMPMCCLKOUT[0] Ball AA10 Y10 W10 DDR / SDRAM data AB11 AA11 Y11 AB6 AA6 DDR / SDRAM chip select Y6 W6 W11 AB12 AB17 AB16 AB15 AB14 Y14 DDR / SDRAM data mask out MPMCDQMOUT[1] MPMCDQMOUT[2] MPMCDQMOUT[3] MPMCDQS[0] MPMCDQS[1] nMPMCCASOUT nMPMCRASOUT nMPMCWEOUT W15 AA19 SDRAM data mask out AA20 AA15 DDR data strobe Y15 Y7 AA7 AB7 LVTTL / SSTL ClassII bidirectional DDR / SDRAM CAS output strobe buffer DDR / SDRAM write enable Voltage reference SSTL / CMOS mode. Analog buffer, 3.3 V This pin is used both as logic state capable and as power supply 32 KHz output crystal 32 KHz input crystal Oscillator 1.2 V capable TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability Output DDR / SDRAM clock enable output DDR / SDRAM output clock 1 LVTTL / SSTL DDR / SDRAM output clock 1 neg. ClassII bidirectional differential DDR / SDRAM output clock 2 buffer DDR / SDRAM output clock 2 neg. LVTTL / SSTL ClassII bidirectional buffer TTL bidirectional buffer, 3.3 V capable, 8 mA drive capability LVTTL / SSTL ClassII bidirectional buffer Direction Function Pin Type
MPMC
MPMCCLKOUT[1] nMPMCCLKOUT[1] MPMCDQMOUT[0]
SSTL_VREF
W14
Input
RTCXO RTC RTCXI
AB5 AB4
Output Input
SMI
SMINCS[0]
G22
Output
Serial Flash chip select
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Table 1.
Group
4 Pin Description
Pin description by functional groups (continued)
Signal Name SMINCS[1] SMINCS[2] SMINCS[3] Ball G21 F22 F21 Serial Flash chip select Direction Function Pin Type TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability TTL bidirectional buffer, 3.3 V capable, 8 mA drive capability TTL bidirectional buffer, 3.3 V capable, 8 mA drive capability, with Pull Up TTL bidirectional buffer, 3.3 V capable, 8 mA drive capability TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability, with Pull Down TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability, with Pull Down TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability, with Pull Down TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability
SMICLK
H20
Output
Serial Flash output clock
SMI SMIDATAIN H21 Input Serial Flash data in
SMIDATAOUT
H22
Output
Serial Flash data out
UART1_RXD
P19
Input
Uart1 RX data
UART1_TXD
P20
Output
Uart1 TX data
UART2_RXD UARTs
P21
Input
Uart2 RX data
UART2_TXD
P22
Output
Uart2 TX data
UART3_RXD
R19
Input
Uart3 RX data
UART3_TXD
R20
Output
Uart3 TX data
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Table 1.
Group
Pin description by functional groups (continued)
Signal Name DMNS DPLS HOST1_DP HOST1_DM HOST2_DP HOST2_DM Ball W1 V1 P1 N1 L1 K1 Direction I/O I/O I/O I/O I/O I/O Function D - port of USB device D + port of USB device D - port of USB host1 D + port of USB host1 D - port of USB host2 D + port of USB host2 TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability Pin Type Analog buffer, 5 V tolerant
HOST1_VBUS
H2
Output
USB host1 VBUS signal
HOST2_VBUS USBs OVERCURH1
H1
Output
USB host2 VBUS signal TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability, with Pull Down TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability TTL bidirectional buffer, 3.3 V capable, 4 mA drive capability, with Pull Down Analog buffer, 3.3 V capable
G1
I/O
USB host1 overcurrent
OVERCURH2
F1
I/O
USB host2 overcurrent
VBUS
H3
I/O
USB device VBUS signal
RREF
K5
Input
USB reference resistor
Table 2.
Group
Pins belonging to POWER group
Signal Name vdde3v3 vdd gnde Ball Note 1 Note 2 Note 3 V22 U18 V21 T18 Ball Digital 3.3 V power Digital 1.2 V power Digitalground Dedicated ADC 3.3 V power Dedicated ADC ground ADC positive reference Voltage ADC pegative reference Voltage Function Function
POWER
vdd3core vsscore VREFP_adc VREFN_adc
Group
Signal Name
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Table 2.
POWER
4 Pin Description
Pins belonging to POWER group (continued)
vdd3core vsscore SSTL_VREF vdde3v3 vdde3v3 vdd gnd gnde vdd3core vsscore vddcore vsscore vddcore vddcore vddcore vdd vddcore vddcore vddcore vddcore vddcore vddcore vdd3core vdde3v3 vdd3core vdd3core vsscore vsscore vsscore gnde gnd vsscore vsscore W7 V7 W14 Note 4 AB2 AA5 AA4 AB3 R2 P4 R4 U2 W3 U4 U3 P2 N5 N3 L4 K4 K3 J4 W4 P5 L3 J3 W5 W2 U5 R3 N4 N2 M2 DDR / SDR dedicated digital PLL 3.3 V power DRR / SDR dedicated digital PLL ground Voltage reference SSTL / CMOS mode. This pin is used both as logic state and as power supply DDR / SDR digital 3.3 / 2.5V power 3.3 V dedicated power for RTC 1.2 V dedicated power for RTC Dedicated digital ground for RTC Dedicated digital ground for RTC Dedicated USB PLL analog 3.3 V power Dedicated USB PLL analog ground Dedicated USB PLL digital 1.2 V power Dedicated USB PLL digital ground Dedicated USB 1.2 V power Dedicated USB 1.2 V power Dedicated USB 1.2 V power Dedicated USB 1.2 V power Dedicated USB 1.2 V power Dedicated USB 1.2 V power Dedicated USB 1.2 V power Dedicated USB 1.2 V power Dedicated USB 1.2 V power Dedicated USB 1.2 V power Dedicated USB 3.3 V power Dedicated USB 3.3 V power Dedicated USB 3.3 V power Dedicated USB 3.3 V power Dedicated USB ground Dedicated USB ground Dedicated USB ground Dedicated USB ground Dedicated USB ground Dedicated USB ground Dedicated USB ground
Note: 1 Signal spread on the following balls: F7, F8, F9, F12, F13, F14, F17, G17 H6, J6, K7, L7, M5, N6, P6, P7,R7, U6, U16. 2 Signal spread on the following balls: F6, F10, F11, F15, F16, G6, H17, J17, K6, L6, M17, N17, R6, T6, T17, U17. 3 Signal spread on the following balls: J9 to J14, K9 to K14, L9 to L14, M9 to M14, N9 to N14, P9 to P14. 4 Signal spread on the following balls: U7 to U15
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4.2
4.2.1
SPECIAL IOs
USB 2.0 Transceiver
SPEAr Head has three USB 2.0 UTMI + Multimode ATX transceivers. One transceiver will be used by the USB Device controller, and two will be used by the Hosts. These are all integrated into a single USB three-PHYs macro.
4.2.2
DRAM
Data and address buses of Multi-Port Memory Controller used to connect to the banks memory are constituted of programmable pins.
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5 Power On Sequence
5
5.1
5.1.1
Power On Sequence
SPEAr Head SW ARCHITECTURE
BOOT PROCESS
Memory mapping A major consideration in the design of an embedded ARM application is the layout of the memory map, in particular the memory that is situated at address 0x0. Following reset, the core starts to fetch instructions from 0x0, so there must be some executable code accessible from that address. In an embedded system, this requires ROM to be present, at least initially.
Serial Flash at 0x0 The SPEAr Head has been designed to use the REMAP concept into its AHB primary bus decoder. The decoder selection for the initial address range (first 64 MB) is conditioned with the content of a AHB remap register, which can be programmed by software at any time. The Serial Flash memory space is accessible in the address range 0x9600_0000 0x99FF_FFFF (64 MB), with or without remap. At reset, before remapping, the Serial Flash memory is 'aliased' at 0x0, which means that the AHB decoder selects the Serial Flash space when accessing the address range 0x0000_0000 to 0x03FF_FFFF. Table 3. Memory mapping at reset - before remapping
SIZE [MB] 64 n. a. 64 DESCRIPTION Serial Flash DRAM Serial Flash (remap)
ADDRESS RANGE 0x9600_0000 - 0x99FF_FFFF Unreachable in this state 0x0000_0000 - 0x03FF_FFFF
DRAM at 0x0 After reset, the boot program makes the remapping, so that the system will be able to access the complete 256 MB of logic memory space associated to DRAM in the range 0x0000_0000 0x0FFF_FFFF. Table 4. Memory Mapping after reset after remapping
SIZE [MB] 64 256 DESCRIPTION Serial Flash DRAM
ADDRESS RANGE 0x9600_0000 - 0x99FF_FFFF 0x0000_0000 - 0x0FFF_FFFF
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5.1.2
BOOTING SEQUENCE
A simple initial description of the boot process is showed in the following steps: 1. 2. 3. Power on to fetch the RESET vector at 0x0000_0000 (from the aliased-copy of Serial Flash). Perform any critical CPU initialization at this time. Load into the Program Counter (PC) the address of a routine that will be executed directly from the non-aliased mapping of Serial Flash (0x9600_0000 + addr_of_routine) and which main objectives are: - - 4. un-map the aliased-copy of the Serial Flash (set REMAP = 1) copy the program text and data into DRAM.
Returning from this routine will set the Program Counter back to DRAM.
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6 IP Description
6
IP Description
In this section you can find the description of the IP's embedded in SPEAr Head.
6.1
ARM926EJ-S
The processor is the powerful ARM926EJ-S, targeted for multi-tasking applications. Belonging to ARM9 general purposes family microprocessor, it principally stands out for the Memory Management Unit, which provides virtually memory features, making it also compliant with WindowsCE, Linux and SymbianOS operating systems. The ARM926EJ-S supports the 32 bits ARM and 16 bit Thumb instruction sets, enabling the user to trade off between high performance and high code density and includes features for efficient execution of Java byte codes. Besides, it has the ARM debug architecture and includes logic to assist in both hardware and software debug. Its main features are: fMAX 266 MHz (downward scalable)

MMU 32 KB of instruction CACHE 16 KB of data CACHE 8 KB of instruction TCM (Tightly Coupled Memory) 8 KB of data TCM AMBA Bus interface Coprocessor interface JTAG ETM9 (Embedded Trace Macro-cell) for debug; large size version.
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ARM926EJ-S block diagram
Figure 2.
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6 IP Description
6.2
6.2.1
CLOCK AND RESET SYSTEM
OVERVIEW
The Clock System is a fully programmable block able to generate every clock necessary at the chip (except for USB 2.0 Host and Device controllers, which have a dedicated PLL); they are:

clock @ 266 MHz for ARM system clock @133MHz for all IPs on AHB Bus clock @ 66.5 MHz for APB Bridge and APB peripherals clock for eASIC MacroCell clock for eASIC Programmable Interface
The block has an embedded PLL, featuring Electro-Magnetic Interference reduction. User has the possibility to set up the PLL in order to add a triangular wave to the VCO clock; the resulting signal will have the spectrum (and the power) spread on a small range (programmable) of frequencies centred on F0 ( VCO Freq.), obtaining minimum electromagnetic emissions. This method replace all the other traditional methods of E.M.I. reduction, as filtering, ferrite beads, chokes, adding power layers and ground planets to PCBs, metal shielding etc., allowing sensible cost saving for customers. Figure 3. Clock System block interfaces
MCLK_in
MCLK_out
PLL_BYPASS
CLOCK SYSTEM
internal clocks
MRESET
The I/O signals accessible from off-chip are listed in Table 5. Clock System I/O off-chip interface: Table 5. Clock System I/O off-chip interface
DIRECTION Input Input Output Input SIZE [bit] 1 1 1 1 DESCRIPTION Oscillator input (12 MHz) External clock in Test mode Oscillator output. It supplies the signal MCLK_in inverted Asynchronous reset
SIGNALS MCLK_in PLL_BYPASS MCLK_out MRESET
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6 IP Description
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The reference clock frequency is 12 MHz and it is used to generate the 266 MHz clock by an internal PLL. Then starting by this, output signals are generated programming the Clock System registers, via APB Bus. The purpose of PLL_BYPASS mainly is let the rest of the chip working properly even in case of PLL failure.
6.2.2
RESET AND PLL CHANGE PARAMETERS SEQUENCE
Figure 4 shows a simplified flow chart of clock system FSM.
The system remains in an IDLE state until RESET signal is asserted: RESET 0. When RESET = 0 the FSM change state and reaches the PLL_PWR-UP state; when PLL locks (PLL_LOCK = 1), means that the PLL_OUT signal oscillates at 264 MHz and the PLL starts to work, so that the FSM advances in the next states. In CLOCK_ENABLED state the clocks can propagate in the system; then the FSM goes in SYSTEM_ON state; it remains in this state in the normal chip working. Figure 4. State Machine of Clock System
To reach at a clock frequency of 266 MHz, PLL had to be appropriately programmed because this frequency isn't an integer multiple of 12 MHz. After this programming, the FSM stops all the clocks and exits from SYSTEM ON state proceeding in PLL SETTING state; here the new parameters are stored in the PLL. If the PLL isn't in Dithered mode the FSM waits for PLL lock, going in LOCK WAIT state, and then will reach SYSTEM ON state when PLL locks.
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6 IP Description
If the PLL is in Dithered mode, the lock signal loses his meaning and there's no need to wait for PLL lock, so the FSM jumps directly from PLL SETTING to SYSTEM ON. When FSM is in SYSTEM ON, all clocks are enabled.
6.3
6.3.1
VECTORED INTERRUPT CONTROLLER
OVERVIEW
The Vector Interrupt Controller provides a software interface to interrupt system, in order to determine the source that is requesting a service and where the service routing is loaded. It supplies the starting address, or vector address, of the service routine corresponding to the highest priority requesting interrupt source. In an ARM system 2 level of interrupt are available:

Fast Interrupt Request (FIQ) for low latency interrupt handling Interrupt Request (IRQ) for standard interrupts
Generally, you only use a single FIQ source at a time to provide a true low-latency interrupt. This has the following benefits:

You can execute the interrupt service routine directly without determining the source of the interrupt It reduces interrupt latency. You can use the banked registers available for FIQ interrupts more efficiently, because you do not require a context save
The interrupt inputs must be level sensitive, active HIGH, and held asserted until the interrupt service routine clears the interrupt. Edge-triggered interrupts are not compatible. The interrupt inputs do not have to be synchronous to AHB clok. The main features of Vectored Interrupt Controller are:

Compliance to AMBA Specification Rev. 2.0 IRQ and FIQ interrupt generation AHB mapped for faster interrupt Hardware priority Support for 32 standard interrupts Support for 16 vectored interrupts Software interrupt generation Interrupt masking Interrupt request status.
Since 32 interrupts are supported, there are 32 interrupt input lines, coming from different sources. They are selected by a bit position and the software controls every line to generate software interrupts; it can generate 16 vectored interrupts. A vectored interrupt can generate only an IRQ interrupt. The interrupt priority is controlled by hardware and it is as follow: 1. 2. 3. FIQ interrupt vectored IRQ interrupt. The higher priority is 0; the lower is 15 non vectored IRQ interrupt
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6 IP Description
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6.3.2
INTERRUPTR SOURCES IN SPEAr Head
Table 6. Interrupt sources in SPEAr Head
Source eASIC0 eASIC1 eASIC2 eASIC3 SPI RTC USB HOST 1 - OHCI USB HOST 2 - OHCI USB HOST 1 - EHCI USB HOST 2 - EHCI USB DEVICE MAC IC GPT4 GPT3 gDMA1 gDMA0 GPT2 GPT1 UART2 UART1 UART0 ADC Reserved Reserved Reserved Reserved Reserved eASIC4 eASIC5 eASIC6 eASIC7 Interrupt Line 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
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6 IP Description
6.4
6.4.1
MULTI-PORT MEMORY CONTROLLER
OVERVIEW
The DRAM interface is controlled by the on-chip Multi-Port Memory Controller. Its main features are:

Supports for SDRAM up to 32 bit wide Supports for DDR up to 16 bit wide Maximum clock frequency 133 MHz 8 AHB port connections 4 chip selects Total addressable memory: 256 MB Maximum memory bank size: 64 MB READ and WRITE buffers to reduce latency Programmable timings Supported memory cuts
Size [MB] Bank Number 2 2 4 4 4 4 4 4 4 4 4 4 4 Row Length 11 11 12 12 11 12 12 12 13 13 13 13 13 Column Length 9 8 9 8 8 10 9 8 10 9 8 11 10
Table 7.
16 (2 MB x 8 bits) 16 (1 MB x 16 bits) 64 (8 MB x 8 bits) 64 (4 MB x 16 bits) 64 (2 MB x 32 bits) 128 (16 MB x 8 bits) 128 (8 MB x 16 bits) 128 (4 MB x 32 bits) 256 (32 MB x 8 bits) 256 (16 MB x 16 bits) 256 (8 MB x 32 bits) 512 (64 MB x 8 bits) 512 (32 MB x 16 bits)
Table 8.
Port 0 1 2 3 4
Multi-Port Memory Controller AHB port assignment
Size [Bit] 32 32 32 32 Priority Max Bus Matrix Reserved eASIC USB 2.0 Device USB 2.0 Host 1 Master
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6 IP Description
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Multi-Port Memory Controller AHB port assignment (continued)
Size [Bit] 32 32 32 Min Priority USB 2.0 Host 2 Ethernet MAC Main AHB System Bus Master
Table 8.
Port 5 6 7
The table is compiled in decreasing order of priority. The I/O interfaces accessible from off-chip are listed here: Table 9. Multi-Port Memory Controller off-chip interfaces
Direction Input Bidirectional Output Output Output Output Output Output Output Output Output Size [Bit] 2 32 2 2 2 4 1 1 1 4 15 Data Strobe Read / write data DRAM clock DRAM inverted clock DRAM clock enable Data mask RAS (active low) CAS (active low) Write Enable (active low) Chip Select (active low) Address Voltage reference SSTL / CMOS mode: SSTL 1.25 V CMOS 0 V This pin is used both as logic state and as power supply. Description
Signal MPMCDQS MPMCDATA MPMCCLKOUT nMPMCCLKOUT MPMCCKEOUT MPMCDQMOUT nMPMCRASOUT nMPMCCASOUT nMPMCWEOUT nMPMCDYCSOUT MPMCADDROUT
SSTL_VREF
Input
1
6.4.2
MULTI-PORT MEMORY CONTROLLER DELAY LINES
As shown in Figure 5, there are 4 DLLs. The CLOCKOUT Delay Line is used to tuner the clock driven from Multi-Port Memory Controller to external DRAM to match setup / hold constraints on external memory. This Delay Lines is used in the "clock delay methodology". The HCLK Delay Lines delays the DRAM command signal (ADDR, CAS, RAS, ...) to capture easily read data from DRAM; this technique is called "command delay". The DQSINL and DQSINH Delay Lines delay respectively the DQS0 (least 8 bit data strobe) and DQS1 (highest 8 bit of data strobe) signals coming from DDR. Delay lines are setting by programming their register through APB Bus.
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Figure 5. Multi-Port Memory Controller DLL
6 IP Description
HCLK
HCLK DLL
HCLK_DLY
DRAM COMMAND DRIVER
ADDR, CAS, RAS, WE, .. DATA_OUT DDR
MPMC
SDR
CLOCKOUT DLL
DATA_IN DQS
DDR
DQSINL DQSINU DLL
6.4.3
SSTLL PIN CONFIGRATION REGISTER
The Stub Series-Terminated Logic (SSTL) interface standard is intended for high-speed memory interface applications and specifies switching characteristics such that operating frequencies up to 200 MHz are attainable. The primary application for SSTL devices is to interface with DDRs. In SPEAr Head THE SSTL pins are:

MPMCDATA[15:0] MPMCADDROUT MPMCCLKOUT nMPMCCLKOUT.
These pins are set through configuration registers on APB Bus.
6.5
SPI MEMORIES
SPEAr Head supports the SPI memory devices Flash and EEPROM. SPI controller provides an AHB slave interface to SPI memories and allows CPU to use them as data storage or code execution. Main features are

SPI master type Up to 20 MHz clock speed in Standard Read mode and 50 MHz in Fast Read mode 4 chip selects Up to 16 MBytes address space per bank Selectable 3-Bytes addressing for Flash and 2-Bytes addressing for EEPROM Programmable clock prescaler External memory boot mode capability
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6 IP Description

SPEAR-09-H022
32, 16 or 8 bit AHB interface Interrupt request on write complete or software transfer complete - - - - - STMicroelectronics M25Pxxx, M45Pxxx STMicroelectronics M95xxx except M95040, M95020 and M95010 ATMEL AT25Fxx YMC Y25Fxx SST SST25LFxx
The compatible SPI memories are:
The I/O interfaces accessible from off-chip are listed here: Table 10. SMC signal interfaces description
Direction Input Output Output Output Size [Bit] 1 1 1 4 Memory input Memory output Clock Bankchip selects (active low) Description
Signal SMIDATAIN SMIDATAOUT SMICLK SMINCS
At power on the boot code is enabled from the static memory Bank0 by default; this has to be a Flash bank memory. Moreover, at power on, the memory clock signal is 19 MHz, the "RELEASE FROM DEEP POWER DOWN" is 29 s and the base address for external memories is 0x0.
6.6
6.6.1
DMA
OVERVIEW
SPEAr Head has 2 DMA Controllers used to transfer data between aASICTM MacroCell and memory. A DMA Controller can service up to 4 data streams at one time; a data transfer consists of a sequence of a DMA data packet transfers. There are two types of a data packet transfer

one is from the source to the DMA Controller one other is from DMA Controller to the destination.
Each DMA Controller has an AHB Master interface to transfer data between DMA Controller and either a source or a destination, and has an APB Slave interface used to program its registers.
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6.6.2
DMA CONTROL STATE MACHINE
Figure 6. DMA State Machine diagram
The DMA control SM is always reset into the IDLE state. As a channel request is asserted, SM moves to READ state and the AHB Master will start a data packet transfer; SM selects appropriate source address. When SM is in WRITE state, it selects the destination address and the data width from the Data Stream register and the AHB Master will transfer all data from the FIFO to the destination. When the AHB Master has transferred the data packet, it asserts a PackEnd signal and the SM will move to the next state, which depends on the channel request signals. The state transitions from the READ or WRITE states can occur only when a whole data packet has been transferred. Figure 7. Data packet transfer
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6.7
6.7.1
USB 2.0 HOST
OVERVIEW
Two blocks drive the USB 2.0 Host interfaces on SPEAr Head. The first is the USB2.0PHY that executes the serialization and the de-serialization and implements the transceiver for the USB line. The second part is the UHC (USB2.0 Host Controller). It is connected on AHB Bus and generates the commands for USB2.0PHY in UTMI+ interface. As there are two USB Hosts, there is one PHY and one UHC for each USB Host port.
6.7.1.1 USB2.0PHY
The USB2.0PHY is a hard macro designed using standard cells and custom cells. In this way has been possible to reach the max speed of USB: 480 Mbits/sec. The block is able to set his speed in LS / FS for USB 1.1 and in HS for USB 2.0.
6.7.1.2 UHC
The UHC is able to detect the USB speed configuration: USB 1.1 (LS / FS), USB 2.0 (HS) via UTMI+ interface. When the speed is detected, the controller uses 2 sub-controllers: EHCI (Enhanced Host Controller Interface) for 2.0 configuration and OHCI (Open Host Controller Interface) for 1.1 configuration. There is an AHB master and a slave for everyone of these controllers.
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6.8
6.8.1
USB 2.0 DEVICE
OVERVIEW
Three blocks drive the USB 2.0 Device interface on SPEAr Head. The first one is the USB2.0PHY, which executes the serialization and the de-serialization and implements the transceiver for the USB line. The second is the UDC (USB 2.0 Device Controller). It is connected on AHB Bus and generates the commands for USB2.0PHY in UTMI+ interface. The last block is the USB Plug Detect, which detects the connection of the device.
6.8.1.1 USB2.0PHY
The USB2.0PHY is a hard macro designed using standard cells and custom cells. In this way is possible to reach the max speed HS of USB: 480 Mbits/Sec.
6.8.1.2 UDC
The UDC is able to detect the USB connection speed via UTMI+ interface. There is an AHB master and three slaves. The UDC contains 6 endpoints (0 control, 1 Bulk IN, 2 Bulk OUT, 3 ISO IN, 4 ISO OUT, 5 Interrupt IN) and 4 configurations.
6.9
ETHERNET MAC 110
The Ethernet Media Access Controller (MAC 110) incorporates the requirements for operation of an Ethernet / IEEE 802.3 compliant node and provides interface between the host system and the Media Independent Interface (which is embedded in SPEAr Head). MAC 110 core features are:

It can operate either in 100 Mbps mode or 10 Mbps mode, depending on the clock provided on the MII interface It can operate both in Half-Duplex mode and Full-Duplex mode. When operating in the Half-Duplex mode, the MAC110 core is fully compliant to Section 4 of ISO / IEC 8802-3 (ANSI / IEEE Standard) and ANSI / IEEE 802.3. When operating in the Full-Duplex mode, the MAC110 core is compliant to the IEEE 802.3x standard for Full-Duplex operations. It is also compatible with Home PNA 1.1.
The MAC110 core provides programmable enhanced features designed to minimize host supervision, bus utilization, and pre- or post-message processing. These features include:

Ability to disable retires after a collision Dynamic FCS generation on a frame-by-frame basis Automatic Pad field insertion and deletion to enforce minimum frame size attributes Automatic retransmission and detection of collision frames.
The MAC110 core can sustain transmission or reception of Minimal-Sized Back-To-Back packets at full line speed with an Inter-Packet Gap (IPG) of 90.6 s for 10 Mb/s and 0.96 s for 100 Mb/s.
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The five primary attributes of the MAC block are: 1. Transmit and receive message data encapsulation - - 2. - - 3. - - 4. 5. Framing (frame boundary delimitation, frame synchronization) Error detection (physical medium transmission errors) Medium allocation (collision detection, except in Full-Duplex operation) Contention resolution (collision handling, except in Full-Duplex operation) Decoding of Control frames (PAUSE command) and disabling the transmitter Generation of Control frames
Media access management
Flow Control during Full Duplex mode
Interface to the PHY - Support of MII protocol to interface with a MII based PHY Management Interface support on MII - Generation of PHY Management frames on the MDC / MDI / MDO.
To minimize the CPU load during the data transfer is available a local DMA with FIFO capable to fetch itself the descriptors for the data blocks and to manage the data according to the instruction included on the descriptor. Figure 8. Block diagram of Ethernet Controller
Local FIFO
MII I/F
AHB Master
DMA RX and TX logic
DATA
MAC block
MIM
AHB Slave Configuration
Conguration register array
6.10
UART
UART provides a standard serial data communication with transmit and receive channels that can operate concurrently to handle a full-duplex operation. Two internal FIFO for transmitted and received data, deep 16 and wide 8 bits, are present; these FIFO can be enabled or disabled through a register. Interrupts are provided to control reception and transmission of serial data.
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The clock for both transmit and receive channels is provided by an internal Baud-Rate generator that divides the AHB Bus clock by any divisor value from 1 to 255. The output clock frequency of baud generator is sixteen times the baud rate value. The maximum speed achieved is 115 KBauds. In SPEAr Head there are 3 UART's, APB Bus slaves.
6.11
I2C
6.11.1 OVERVIEW
The controller serves as an interface between the APB Bus and the serial I2C bus. It provides master functions, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. Supported Standard (100 KHz) and Fast (400 KHz) I2C mode. Figure 9. I2C Controller block diagram
SLC Control APB BUS APB Interface Register Array SDA Control IC BUS
Main features are:

Parallel-bus APB / I2C protocol converter Standard I2C mode (100 KHz) / Fast IC mode (400 KHz) Master interface (only). Detection of bus errors during transfers Control of all I2C bus-specific sequencing, protocol, arbitration and timing
In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa, using either an interrupt or a polled handshake. The interrupts can be enabled or disabled by software. The interface is connected to the I2C bus by a data pin (SDA) and by a clock pin (SCL). SDA signal is synchronized by SCL signal.
6.11.2 I2C OPERATING MODE
Communication flow In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated by software.
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The first byte following the start condition is the address byte; it is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Figure 10. I2C timing
Acknowledge may be enabled and disabled by software. The I2C interface address and / or general call address can be selected by software. The speed of the I2C interface may be selected between Standard (0 - 100 KHz) and Fast (100 - 400 KHz).
SDA / SCL Line Control Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data Register. Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register. The SCL frequency (FSCL) is controlled by a programmable clock divider which depends on the I2C bus mode. When the I2C cell is enabled, the SDA and SCL ports must be configured as floating open-drain output or floating input. In this case, the value of the external pull-up resistance used depends on the application.
6.11.3 I2C FUNCTIONAL DESCRIPTION
Master Mode The I2C clock is generated by the master peripheral. The interface operates in Master mode through the generation of the Start condition: Start bit set to 1 in the control register and IC not busy (Busy flag set to 0). Once the Start condition is sent, if interrupts are enabled, an Event Flag bit and a Start bit are set by hardware. Then the master waits for a read of the register used to observe bus activity (SR1 register) followed by a write in the data register DR with the Slave address byte, holding the SCL line low (see Figure 11 Transfer sequencing EV5). Then the slave address byte is sent to the SDA line via the internal shift register.
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After completion of these transfers, the Event Flag bit is set by hardware with interrupt generation. Then the master waits for a read of the SR1 register followed by a write in the control register CR (for example set the Peripheral Enable bit), holding the SCL line low (see Figure 11 Transfer sequencing EV6). Next the Master must enter Receiver or Transmitter mode.
Master Receiver Following the address transmission and after SR1 and CR registers have been accessed, the Master receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: 1) Acknowledge pulse if the acknowledge bit ACK in the control register is set 2) Event Flag and the Byte Transfer Finish bits are set by hardware with an interrupt. Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 11 Transfer sequencing EV7). To close the communication: before reading the last byte from the DR register, set the Stop bit to generate the Stop condition. In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte.
Master Transmitter Following the address transmission and after SR1 register has been read, the Master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 11 Transfer sequencing EV8). When the acknowledge bit is received, the interface sets Event Flag and the Byte Transfer Finish bits with an interrupt. To close the communication: after writing the last byte to the DR register, set the Stop bit to generate the Stop condition.
Error Cases

BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the Event Flag and BERR bits are set by hardware with an interrupt. AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt. To resume, set the Start or Stop bit.
In all these cases, the SCL line is not held low; however, the SDA line can remain low due to possible 0 bits transmitted last. It is then necessary to release both lines by software.
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Figure 11. Transfer sequencing
Legend: S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge EVx=Event (with interrupt if ITE=1) EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1). EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
6.12
GENERAL POURPOSE I/Os
The GPIO block consists of 6 General Purpose IOs which act as buffers between the I/O pins and the processor core: data is stored in the GPIO block and can be written to and read from by the processor via the APB Bus. Figure 12. GPIO block diagram
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6.13
ADC
6.13.1 OVERVIEW
The ADC-APB Bus controller provides connection between APB Bus and ST-ADC8MUX16 Analog to digital Converter: it handles the acquisition request from APB Bus and generates control and configuration signals to drive ADC and also the interrupt signal when acquisition is ready. For any ADC input channel the controller can realize a single acquisition or an average up to 128 samples. There are two operating mode:

Normal mode: it handles all the digital ports of ST-ADC8MUX16. Test mode: the ST-ADC8MUX16 is directly accessible by means of external pins as a stand-alone ADC. This will allow stand-alone testing procedures (digital and analog) - - positive VREFP_adc pin negative VREFN_adc pin
ADC positive and negative reference voltages are supply by:
6.13.2 ADC OPERATING MODES
Normal mode When the enable bit is set to 1, the conversion starts and as it finishes a bit of Conversion Ready (interrupt signal) is set to 1. At this point the reading of the data could begin and when it finishes, Conversion Ready and the enable bits becomes 0. In Normal mode the signals accessible off-chip are listed in Table 11 External pins of ADC macro in Normal mode. Table 11. External pins of ADC macro in Normal mode
Direction Input Description Analog channels
Signal AID[15:0]
Test mode Test mode is set by assigning the following logic state to the test pins: TEST0 0 TEST1 1 TEST2 0 TEST3 1 In this mode ST-ADC8MUX16 is accessible for the testing procedure and its signals are switched to the following pins:
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External pads of ADC macro in Test mode
PIN TEST_OUT TX_EN CRS COL RXD[0] SCL RXD[1] RXD[2] RXD[3] RX_DV RX_ER MCD MDIO SDA TX[0 to 3] DIRECTION Output Input Input Input Input Output Output Output Output Output Output Output Output Output Input DESCRIPTION Analog test point output Test mode select Start conversion Conversion enable Clock End of conversion Data output Data output Data output Data output Data output Data output Data output Data output Selection line - input analog mux
Table 12.
SIGNAL TEST_OUT TEST START EN CLK EOC D_0 D_1 D_2 D_3 D_4 D_5 D_6 D_7 SEL[0 to 3]
6.14
WATCHDOG TIMER
The WdT is based on a programmable 8 bit counter and generates a hot reset (single pulse) when it overflows. The timer should be cleared by the software before it overflows. The counter is clocked by a slow signal coming from a 21 bit prescaler clocked by the APB clock. So that, as APB Bus has a frequency of 66.5 MHz, the maximum elapsing time is 8.07 second, while the minimum is 31.52 ms. The WdT is an APB Slave device.
6.15
REAL TIME CLOCK
The Real Time Clock block implements 3 functions:

time-of-day clock in 24 hour mode calendar alarm
Time and calendar value are stored in binary code decimal format. Date and time are stored in dedicated registers, so that the RTC can start to count the time. An alarm time can be defined and when the value of time and date is equal to the value on alarm registers, an interrupt is generated, if enabled. For debug the prescaler, that define the seconds, they can be bypassed to obtain a faster counter of the time.
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A further option available is that if the seconds are masked, an interrupt for any second is generated. In the same way for minutes, hours, days, months or years. The RTC provides also a self-isolation mode, which allows it working even if power isn't supplied to the rest of the device. The RTC is an APB Bus.
6.16
GENERAL POURPOSE TIMER
SPEAr Head has 4 GPTs, connected as APB Bus slaves. A GPT is constituted by 2 channels and each one consists of a programmable 16 bit counter and a dedicated 8 bit timer clock prescaler. The programmable 8 bit prescaler unit performs a clock division by 1, 2, 4, 8, 16, 32, 64, 128, and 256, allowing a frequency range from 3.96 Hz to 66.5 MHz. Two modes of operation are available for each GPT:
Auto Reload Mode. When the timer is enabled, the counter is cleared and starts incrementing. When it reaches the compare register value, an interrupt source is activated, the counter first is automatically cleared and then restarts incrementing. The process is repeated until the timer is disabled. Single Shot Mode. When the timer is enabled, the counter is cleared and starts incrementing. When it reaches the compare register value, an interrupt source is activated, the counter stopped and the timer disabled. The current timer counter value could be read from a register.
6.17
CUSTOMIZABLE LOGIC
6.17.1 OVERVIEW
The Customizable Logic consists of an embedded macro where it is possible to map up to 200K equivalent ASIC gates. The logic is interfaced with the rest of the system so that it is possible to implement:

AHB sub-systems with masters and slaves (via 1 AHB full master, 1 AHB full slave, 1 AHB master lite, 2 AHB slave ports) AHB master lite connected to DRAM controller AHB memories (via AHB slave ports) implemented by configuring the logic cells as SRAM elements. I/O protocol handlers (via the 112 dedicated GPIO connections) 8 interrupt channels 8 DMA requests 4 independent SRAM data channels (via dedicated connection to on-chip 16 KByte SRAM)
All of the above configuration scenarios can be mixed together in the same user-defined logic.
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6.17.2 CUSTOM PROJECT DEVELOPMENT
The custom project to design in the customizable logic can be implemented on an external FPGA, which emulates eASIC logic cells. The purpose of this characteristic is allowing the user to develop his project both under real-time constraints and compliant to eASIC MacroCell features. This mode is enabled by using the GPIO interface, which is internally configured to support fullmaster and full-slave AHB ports. The Figure 13 highlights the described behavior. In order to enable the "Development mode", the configuration pin has to be set to state logic 1. After this configuration the logic implemented in the external FPGA
can completely interact with the following scenarios: - - - - AHB sub-systems with masters and slaves connected to the main system bus (full masters and full slaves peripherals) I/O protocol handlers (via 112 dedicated FPGA I/Os) 4 interrupt channels 4 DMA requests
All the above scenarios can be mixed in the same FPGA configuration
can be tested in order to verify the accordance with eASIC MacroCell features, by running the ARM926EJ-S software debugger on a PC connected to SPEAr Head. Once this test has been completed successfully, then the user-defined logic is ready to be moved without any additional changes within the on-chip eASIC configurable logic
Figure 13. Emulation with external FPGA
SPEArTM Head
Configuration pad set to
Development Mode
AHB BUS
FPGA Custom Design
eASICTM
6.17.3 CUSTOMIZATION PROCESS
The customization process requires two separate steps, executed at different times: 1. Programming layer fabrication (single VIA-mask). 2. Bitstream download.
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The step 1 defines the interconnection between the customizable logic cells and is executed at fabrication level on top of the silicon wafers stored in the fab. The step 2 defines the logic function for each customizable logic cell and is executed after that the system has been powered up by dedicated software routines running on the ARM926 microprocessor. Both Bitstream and VIA-mask realize the user-defined customization for the entire device. The eASIC mapping flow starts from the RTL description of the user-defined customization, with the purpose to generate the VIA-mask and configuration Bitstream.
6.17.4 POWER ON SEQUENCE
Once the system is powered-on, the eASIC logic has to be properly configured before its usage. In order to accomplish this task, two main operations have to be performed (both using dedicated software routines running on the ARM9 microprocessor): 1 Bitstream download 2 Startup of connection between the eASIC MacroCell and the rest of the device Both steeps are driven by a control register programmable via APB Bus.
6.17.5 BITSTREAM DOWNLOAD
The bitstream download operation is responsible for the eASIC logic initialization, since each configurable cell of the customizable logic is loaded with a data stream that represents the mapped logic function. Each operation of this download is performed by a dedicated software routine that read and writes data across the Control register. The bitstream is a 32 KByte data that is stored in the external non-volatile memory of the SPEAr device.
6.17.6 CONNECTION STARTUP
Once the eASIC logic is up and running due to the Bitstream initialization, next steep is its reset, in order to allow connections to the other IPs of the chip. The reset routine is activated by programming the Control register. Last steep is the enabling of needed connections, by setting the Status register.
6.17.7 PROGRAMMING INTERFACE
In order to achieve the Bitstream download and the reset routine, a dedicate logic has been embedded in the SPEAr Head: the Programming Interface, which also includes the Control register.
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7
7.1
Electrical Characteristics
ABSOLUTE MAXIMUM RATINGS
This product contains devices to protect the inputs against damage due to high static voltages; however it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. Table 13.
Symbol VDD core VDD I/O VDD PLL VDD SDR VDD DDR VDD RTC Vi TTL Vi SRAM Vi DDR Vi USBds Vi USBrr Vi AN Tj Tstg Supply voltage core Supply voltage I/O Supply voltage PLL Supply voltage SDRAM Supply voltage DDR Supply voltage RTC Input voltage TTL (3.3 and 5 V tollerant) Input voltage SDRAM Input voltage DDR Input voltage USB (Host and Device) data signal interfaces Input voltage USB reference resistor Analog input voltage ADC Junction temperature Storage temperature
Absolute maximum rating values
Parameter Value 2.1 6.4 6.4 6.4 5.4 2.1 6.4 6.4 5.4 6.4 6.4 6.4 -40 to 125 -55 to 150 Unit V V V V V V V V V V V V C C
The average chip-junction temperature, Tj, can be calculated using the following equation: Tj = TA + (PD * JA) where : TA is the ambient temperature in C JA is the package Junction-to-Ambient thermal resistance, which is 34 C/W
PD = PINT + PPORT - PINT is the chip internal power - PPORT is the power dissipation on Input and Output pins ; user determined
If PPORT is neglected, an approximate relationship between PD is: PD = K / (Tj + 273 C) And, solving first equations: K = PD * (TA + 273 C) + JA x PD2 K is a constant for the particular, which can be determined through last equation by measuring PD at equilibrium, for a know TA Using this value of K, the value of PD and TJ can be obtained by solving first and second equation, iteratively for any value of TA.
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7.2
7.2.1
DC ELETTRICAL CHARACTERISTICS
SUPPLY VOLTAGE SPECIFICATIONS
The recommended operating conditions are listed in the following table: Table 14.
Symbol VDD core VDD I/O VDD PLL VDD SDR VDD DDR VDD RTC Top
Recommended operating conditions
Description Supply voltage core Supply voltage I/O Supply voltage PLL Supply voltage SDRAM Supply voltage DDR Supply voltage RTC Operating temperature Min. 1.14 3 3 3 2.3 1.14 -40 Typ. 1.2 3.3 3.3 3.3 2.5 1.2 Max. 1.26 3.6 3.6 3.6 2.7 1.26 85 Unit V V V V V V C
7.2.2
I/O VOLTAGE SPECIFICATIONS
7.2.2.1 LVTTL I/O (C0MPLIIANT WITH EIA/JEDEC STANDARD JESD8-B)
For LVTTL (3.3 and 5 V tolerant) pins, the allowed I/O voltages are: Table 15.
Symbol Vil Vih Vhyst
Low Voltage TTL DC input specification (3 < VDD < 3.6)
Parameter Low level input voltage High level input voltage Schmitt trigger hysteresis 2 0.495 0.620 Test Condition Min. Max. 0.8 Unit
V V V
Table 16.
Symbol Vol Voh
Low Voltage TTL DC output specification (3 < VDD < 3.6)
Parameter Low level output voltage High level output voltage Test Condition Iol = X mA * Ioh = X mA * VDD - 0.15 Min. Max. 0.15 Unit V V
* X is the source / sink current under worst case conditions and it is reflected in the name of the I/O cell according to the drive capability.
Table 17.
Symbol Ipu Ipd Rup Rpd
Pull-up and Pull-down characteristics
Parameter Pull-up current Pull-down current Equivalent Pull-up resistance Test Condition Vi = 0 V Vi = VDD Vi = 0 V Min. 40 30 32 27 Typ. 60 60 50 50 Max. 110 133 75 100 Unit A A KOhm KOhm
Equivalent Pull-down resistance Vi = VDD
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7.2.2.2 LVCMOS/SSTL I/O
If the I/Os are set as LVCMOS (for SDRAM memories), the DC electrical characteristics are the following: Table 18.
Symbol Vil Vih Iin
LVCMOS DC input specification (3 < VDD < 3.6)
Parameter Low level input voltage High level input voltage Input Current Vin = 0 or Vin =VDD Test Condition Vout Voh (min) or Vout Vol (max) Min. -0.3 2 Max. 0.8 VDD+0.3 5 Unit V V A
Table 19.
Symbol Vol Voh
LVCMOS DC output specification (3 < VDD < 3.6)
Parameter Low level output voltage High level output voltage Test Condition VDD = min, Iol = 100 A VDD = min, Ioh = -100 A VDD - 0.2 Min. Max. 0.2 Unit V V
Instead when they are set as (for DDR memories), refer to following tables: Table 20.
Symbol Vil Vih
DC input specification of bidirectional SSTL pins (2.3 < VDD DDR < 2.7)
Parameter Low level input voltage High level input voltage Min. -0.3 SSTL_VREF + 0.15 Max. SSTL_VREF - 0.15 VDD DDR - 0.15 Unit V V
Table 21.
Symbol Vil Vih
DC input specification of bidirectional differentialSSTL pins (2.3 < VDD DDR < 2.7)
Parameter Low level input voltage High level input voltage Min. -0.3 0.36 Max. VDD DDR + 0.3 VDD DDR - 0.6 Unit V V
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8 Package information
8
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 14. PBGA420 Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 A2 b D D1 D2 E E1 E2 e F ddd eee fff 22.80 0.50 22.80 0.30 1.53 0.60 23.00 21.00 20.00 32.00 21.00 20.00 1.00 1.00 0.20 0.25 0.10 0.039 0.039 0.008 0.010 0.004 23.20 0.70 0.020 TYP. MAX. 2.16 0.012 0.060 0.024 0.027 0.913 MIN. TYP. MAX. 0.085 inch
OUTLINE AND MECHANICAL DATA
23.20 0.8976 0.905 0.827 0.787
PBGA420 (23x23x2.16mm) Ball Grid Array Package
7740354 A
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Revision history
Date 17-Oct-2005 1-Dec-2005 Revision 1 2 Initial release. Changed the Part Number from SPEAR-09-H020 to SPEAR-09-H022. Modified/added some dates in the Chapter 7. Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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